1. Field of the Invention
The present invention relates to a data transmitting/receiving buffer such as a USB (Universal Serial Bus). More particularly, the present invention relates to a test circuit thereof. This application is counterpart of Japanese patent applications, Serial Number 24164/2002, filed Jan. 31, 2002, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A USB is an interface to connect peripheral devices such as a keyboard, a mouse, a modem and a printer to a personal computer (hereinafter, referred to as PC) using the same connectors and the same cables. As a result of strategy by each company of COMPAC, INTEL, MICROSOFT and NATIONAL SEMICONDUCTOR, a formal specification is disclosed as USB 1.0 in February, 1996.
According to the USB, 127 functions (peripheral devices) can be connected to one host (one personal computer) at the maximum. In adjustment for a bus, the host manages the adjustment and the only function to which a token is issued from the host can access to this host. The host is connected to the function by means of a half-double connection. A high speed mode, which is 12 Mbps at the maximum and a low speed, which is 1.5 Mbps are mixed in a data transfer speed.
FIG. 2 is a diagram of configuration showing connection of a PC to a peripheral apparatus by a conventional USB.
A personal computer 10 and a peripheral apparatus 20 are connected to each other by a dedicated cable 30 whose both ends are connected to connectors. In the PC 10 is provided with a USB buffer 11 to transmit/receive data to/from the peripheral apparatus 20 and a power supply 12 to supply an electric power to the peripheral apparatus side. In a peripheral apparatus 20 there is provided a USB buffer 21 to transmit/receive data to/from the personal computer 10 via the cable 30 and a power supply 22 to supply the electric power supplied from the personal computer side to the inside the peripheral apparatus.
A configuration of USB buffer 11 of the PC 10 is similar to the USB buffer 21 of the peripheral apparatus 20. Each of the USB buffer 11 and the USB buffer 21 have nodes 1a, 1b, a differential receiver 2, single end receivers 3a, 3b and a differential driver 4.
Nodes 1a, 1b are terminals to be connected to differential signals D+, Dxe2x88x92 on the cable 30. The differential receiver 2 is connected to the nodes 1a, 1b and outputs receiving data RD based on potentials of the differential signals D+, Dxe2x88x92. When the signal D+ is a xe2x80x9cHxe2x80x9d level (4V) and the signal Dxe2x88x92 is an xe2x80x9cLxe2x80x9d level (0V), the receiving data RD output from the differential receiver 2 becomes xe2x80x9cHxe2x80x9d. When the signal D+ is xe2x80x9cLxe2x80x9d and the signal Dxe2x88x92 is xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d, the receiving data RD becomes xe2x80x9cLxe2x80x9d.
The single end receivers 3a, 3b are buffer amplifiers having configurations, which are Schmitt trigger circuits. The single end receivers 3a, 3b have a hysteresis characteristic that an output signal becomes xe2x80x9cHxe2x80x9d when an input signal exceeds a threshold value of the top side (2V), and the output signal becomes xe2x80x9cLxe2x80x9d when the input signal lowers to less than a threshold value of the bottom side (0.8V). Input parts of the single end receivers 3a, 3b are respectively connected to the nodes 1a, 1b, and signals SE0, SE1 are output from the single end receivers 3a, 3b. 
The differential driver 4 consists of 3-state-type buffer amplifiers 4a, 4b, the differential driver 4 outputs data when an output enable signal/OE is xe2x80x9cLxe2x80x9d, and an output part becomes a high impedance when an output enable signal/OE is xe2x80x9cHxe2x80x9d. Transmitting data TD are supplied to an input part of the buffer amplifier 4a and the output part of the buffer amplifier 4a is connected to the node 1a. The transmitting data/TD where the transmitting data TD is inverted are supplied to the input part of the buffer at a time of transmitting data, and a signal FSC of xe2x80x9cLxe2x80x9d is supplied at a time where transmission is finished. The output part of the buffer amplifier is connected to the node 1b. 
The nodes 1a, 1b in the USB buffer 11 at the PC 10 side respectively are pulled down with a resistance of 1.5xcexa9. At the peripheral apparatus 20 side, the node 1a is pulled up with the resistance of 1.5xcexa9 in a high speed mode, and the node 1b is pulled up with the resistance of 1.5xcexa9 in a low speed mode (not shown in FIG. 2).
To transfer data with less error at a high speed using such a USB, waveforms of the differential signals D+, Dxe2x88x92 transmitted on the cable 30 are accurately defined.
FIG. 3 is a view showing standard of USB signal waveform in the high speed mode. In FIG. 3, an x-axis and a y-axis respectively show a time and a voltage, and FIG. 3 defines speeds to rise and fall the differential signals D+, Dxe2x88x92 and standardization of levels of xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d. It is necessary not to enter waveforms of the differential signals D+, Dxe2x88x92 corresponding to one element into a reversed portion (eye in a hexagon shape, i.e., eye pattern) in FIG. 3.
When characteristics of the USB buffers 11, 21 are tested, for example, the eye pattern of the differential signals D+, Dxe2x88x92 is observed in a state where the PC 10 is connected to the peripheral apparatus 20 by the cable 30, and an oscilloscope is connected to the nodes 1a, 1b of the USB buffer 21.
However, in the conventional USB buffers 11, 21 there is a problem in that there is no signal except for the differential signals D+, Dxe2x88x92 as a signal, which is trigger when the differential signals D+, Dxe2x88x92 of the nodes 1a, 1b are observed by the oscilloscope. Therefore, for example, the oscilloscope displays the eye pattern as trigger, which is timing of rise of the signal D+. However, since two-ways communication of half-double is performed in the USB, it is not possible to identify whether an observed waveform is a receiving signal or a transmitting signal. Therefore, there is a problem that in a case where a signal waveform does not meet standardization, it is not possible to specify that either a transmitting operation or a receiving operation has default.
Therefore, it is an object to provide a data transmitting/receiving buffer such as a USB capable of selecting waveforms of a transmitting signal and a receiving signal to observe the selected waveform, which are capable of overcoming the above drawbacks accompanying the conventional art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to a first aspect of the present invention, a data transmitting/receiving buffer for transmitting/receiving data via a data line provided between a first apparatus and a second apparatus, includes: a receiver which receives a signal on the data line and which outputs the receiving data; a driver which outputs transmitting data to the data line when a transmitting enable signal is supplied; and a transmitting signal trigger output circuit which outputs a transmitting trigger signal based on the transmitting enable signal and the transmitting data.
According to the first aspect, since the data transmitting/receiving buffer is configured as described above, the data transmitting/receiving buffer has the following function.
When the transmitting enable signal and the transmitting data are supplied at a time of output, the signal is transmitted from the driver to the data line, and the transmitting trigger signal is output from the transmitting trigger output circuit based on this output. Therefore, by observing the signal on the data line as trigger, which is the transmitting trigger signal with the oscilloscope, it is possible to select the only transmitting signal to observe the selected signal.
According to a second aspect, a data transmitting/receiving buffer for transmitting/receiving data via a data line provided between a first apparatus and a second apparatus, includes: a receiver which receives a signal on the data line and which outputs the receiving data; a driver which outputs transmitting data to the data line when a transmitting enable signal is supplied; and a receiving signal trigger output circuit which outputs a receiving trigger signal based on the transmitting enable signal and the receiving data.
According to the second aspect of the present invention has the following function.
When the signal on the data line is received by the receiver and the receiving data are output at a time of input, the receiving trigger signal is output from the receiving trigger output circuit on this input. Therefore, by observing the signal on the data line as trigger, which is the receiving trigger signal with the oscilloscope, it is possible to select the only receiving signal to observe the selected signal.
According to a third aspect, the data line is a universal serial bus.
According to a fourth aspect, the data line is a universal serial bus.
According to a fifth aspect, the receiver is a differential-type receiver which receives a differential signal on the universal serial bus.
According to a sixth aspect, the data transmitting/receiving buffer provides a receiver, a driver and a transmitting trigger output circuit similar to the first aspect; and a receiving trigger output circuit similar to the second aspect.
According to the sixth aspect, the transmitting trigger signal is output from the transmitting trigger output circuit at the time of output and the receiving trigger signal is output from the receiving trigger output circuit at the time of input. Therefore, by observing the signal on the data line with the oscilloscope as trigger, which is the transmitting trigger signal or the receiving trigger signal, it is possible to select one of the transmitting signal or the receiving signal to observe the selected signal.
According to a seventh aspect, the driver is a differential-type driver which converts the transmitting data into the differential signal and which outputs the converted differential signal on the data line.
According to an eighth aspect, the driver is a differential-type driver which converts the transmitting data into the differential signal and which outputs the converted differential signal on the data line.
According to a ninth aspect, a data transmitting/receiving buffer for transmitting/receiving data via a data line provided between a first apparatus and a second apparatus, includes: a receiver which receives a signal on the data line and which outputs the receiving data; a driver which outputs transmitting data to the data line when a transmitting enable signal is supplied; and a transmitting signal trigger output circuit which outputs a transmitting trigger signal based on the transmitting enable signal and the transmitting data; and a receiving signal trigger output circuit which outputs a receiving trigger signal based on the transmitting enable signal and the receiving data.
According to a tenth aspect, the data line is a universal serial bus.
According to ninth and tenth aspects have the following functions.
When the transmitting data is transmitted to the data line by the driver at the time of output, the transmitting signal is received by the receiver and the receiving data are output. The transmitting enable signal is held at timing where the receiving data is changed and the held transmitting enable signal is output from the trigger output circuit as the trigger signal.
At the time of input, the signal on the data line is received by the receiver and the receiving data are output. The transmitting enable signal is held at timing where the receiving data is changed and the held transmitting enable signal is output from the trigger output circuit as the trigger signal.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.